Universal
Adapter of Analog-Digital I/O for IBM PC
NVL 03.1
Òåchnical
Description:
1. Introduction
This description is included in a set with the device NVL03.1 and
is an important document for the usage of this device.
1.1. The producer has a right to make changes in the scheme which
are not followed by any changes in the parameters of the usage
of this device.
2. Application
NVL031 is designed for working in the PC slot of the
IBM PC XT - Pentium III type. The device executes analog signals
conversion in the voltage range +/-5 V and in frequency range
0-12 kHz to digital signals.
3. Functions of
The Device
-
3.1. Analog data input
-
3.2. Digital data input
-
3.3. Digital data output
4.
Òåchnical Characteristics
- 4.1.
Ànalog Input
| ADC chip |
Ê1113PV1 |
| Number of channels |
16 |
| Resolution |
10 bit |
| Input voltage ranges |
+/-1.0;+/-1.25;+/-2.5;+/-5V |
| Maximum input voltage |
+/- 12V |
| Conversion time |
upto 30 ms |
| Minimum selection time
(interval) |
upto 33 ms |
| ADC start intervals change
with differentiation: |
1 ms |
| Channel commutator installation
time |
upto 0.3ms |
| Maximum frequency
range level of input signals (0.8 from Nikevist frequency) |
12.5 kHz. |
| Minimum frequency range
level of input signals |
0 Hz |
| Channel switching/ADC
start time interval |
upto 5 ms |
| Voltage measurement mistake |
+/- 0.25 % |
| Time interval mistake |
0.000001 % |
Start mode: apparatus; interval is programmable; program of
external. ADC results receiving: program (waiting for readiness),
on interruption.
4.2. Digital I/O
Digital I/O provides an opportunity of program connection
to 2 independent registers which work in the mode of I/O.
4.3 IBM PC Bus
Cooperation
The device requires a volume of 20 addresses in the
space of I/O.
The
basic address is chosen by
a jumper on the card
The basic addresses may be: 200Í, 220Í, 300Í.
interruptions: IRQ3, IRQ5, IRQ7.
5.
Structure Scheme and Work of NVL03.1
5.1 As for functions NVL031 may be devided to 2 independent parts:
ADC and digital I/O. As for ADC it consists of two following parts:
-
input amplifier (A2), provides
high input impedance and a normal coefficient of amplifying
-
the device of selection and storage maintains
stabil voltage on the chip input of the ADC during the conversion
time. This voltage is the same as normal voltage of NVL031
input voltage at the moment of starting the analog/digital converter
-
schemes of starting which form
the signals are necessary for the work of ADC, SHA chips and the
signals which maintain cooperation of the PC and NVL031.
The major element of the scheme of starting is a programmable
timer ÊP580VI53. Two channels of this timer 1 and 0 form
the length of intervals between apparatus starting and intervals
of delay in case of program or external starting. Frequency
CLKÒ = 2 ÌHz is transferred to the timer input so the minimum
discret of the intervals formed by the timer is 1 ms and maximum
interval of the apparatus formed time is about 1,3 s.
*Ìinimum time interval between
startings should not be less than ADC convertion time (not less
than 30ms)
*Ìàximum number that can be written to the 0 channel counter in
case of apparatus start should be upto 20.
Apparatus start is executed independent from the bus work;
the accuracy is maintained by a crystal oscillator. After every
conversion the ADC forms the impulse of readiness which may be waited
for by a program or if it is required can be used as a signal of
interruption. During this maximum speed of NVL031 work is maintained.
The reason is that PC data capture is executed at the time when
ADC has already begun its next conversion.
Program starting is executed by programming the timer to form
a single impulse. To execute external starting there is an output
"start". Log 1 - impulse forming permitted; Log 2- impulse
forming banned.
5.2 The scheme of starting uses two out of three timer channels.
The third can be used by the user.
5.3 There is a programmable integrated I/O port ÊÐ580ÂÂ55À(Intel
8255) in NVL031for digital I/O. Two ÊÐ580ÂÂ55À registers:
A and B are available for the user.
6. NVL031
Programming.
6.1. The registers execute program connection for NVL031control
and for data exchange. These registers are situated in the address
space of I/O of the IBM PC. To use several NVL031devices in
one IBM PC and to prevent an address "conflict" with other
devices which are used in the IBM PC there is an opportunity of
switching the addresses in NVL031. There are 3 basic addresses which
can be set in NVL031(by the jumper): 200h, 220h, 300h. The address
of any register in the address space of IBM PC is easy to find out.
You need to count the basic address plus the address of the register.
6.2. To execute the control of the device NVL031 there is a register
of orders. Its adress is 0Ch. The 0 adress of this register maintains
the functioning of the start scheme. Logical 0 in this case banns
ADC starting and logical 1 permits it. The second bit of the order
register puts the ADC starting scheme at the very first position.
To do this it is necessary to set log "0" in this bit
before starting your work and then log "1"and maintain
it during the whole period of the ADC work. The other bits of this
register should be kept in log "1" position.
6.3. As it has already been mentionned the central element of the
starting scheme is a proggrammable integrated timer ÊR580VI53.
The registers' adresses of this timer are:
channel 0 - 00h
channel 1 - 01h
channel 2 - 02h
register of control - 03h
The device NVL031 permits 3 possible variants of ADC start.
- àpparatus - in this mode a timer forms the start impulses. For
this purpose it is necessary to program timer channels: channel
1 and channel 0 for working in the mode 2 (impulse generator). Intervals
between ADC starts are like the following:
Ò = N1 * N0
Ò - interval between the ADC starts (ms.).
N1 - number written in channel 1 of the timer.
N0 - number written in channel 0 of the timer
T should be not less than 30. Number 2 in mode 2 can not be downloaded.
If N0 and N1 are chosen it is necessary to follow the rule:
N0 should be maximum. If starting is executed by the apparatus 0
bit of the order register should be in log. ''1'' position. If starting
is executed by the program then the program regards it as ADC starting. Channel 0 of the timer is programmed for working in mode 1, number
3 is written in it as for the 1st channel number 2 is written in
it. After this every changing from position "0" to "1"
will be followed by ADC start. Externally everything is the same
as in the apparatus type; the only difference is that 0 bit of the
order register should be in log."1" position; ADC starting
begins after every positive change at "SE" contact of
the input. It should be mentioned that starting with some delay
is also possible.
6.4. There is a programmable integrated I/O port ÊÐ580ÂÂ55À ( Intel
8255) used in NVL031. Two registers of this port (A and B) are available
for a user as I/O ports. Register C is used in the following way:
minimum 4 (0-3) bits identify (in 2(bi) code) the number of the
ADC channel, 6 bit (bit5) is a signal of ADC readiness. To execute
these functions register C is devided into 2 parts: minimum for
output and maximum for input. The following register adresses of
the programmable integral I/O port ÊÐ580ÂÂ55À(Intel 8255)are used
in NVL03 :
register À 04h
register  05h
register Ñ 06h
controlling register 07h
6.5. The result of AD conversion are received serially; the period
of receiving is devided into 2 parts: reading from the register
with 08h address: first maximum byte(bits "0" and "1"
where are "8" and "9" bits of the ADC code)
then minimum. The other bits of the maximum byte are not identified
and should be made 0 after receiving the maximum byte
There are two types of receiving the results in NVL03:
-
Program: when
the program evaluates bit 5 of the register C. It is connected
with the signal of readiness of the ADC chip. After starting
the AD conversion this bit is transmitted to log."0"
position and is left like this till the end of this conversion.
Changing from position log."0"to log. "1"
means that the ADC code has been rewritten to the output buffer.
It is necessary to mention that the structure of NVL031 is designed
in such a way that the results of the previous AD conversion
are left in the output buffer during the whole period of the
next conversion and consequently it can be read any time. This
is really an advantage when you execute the capture
of interruption data to maintain maximum speed. It can be explained
by the fact that during the ADC start the processor does
not spend any time to organise waiting for readiness instead
of this it executes conversion of the data received before.
-
On
Interruption: to use this opportunity it is necessary to chose one of the
free interruptions of your PC (with the help of a jumper): IRQ3,
IRQ5 or IRQ7 and write a program of interruption processing
that will include capture of the results of the previous AD
conversion. NVL031 makes an interruption signal after every
ADC.
Full
description of NVL031 with a sample of programming
