Card NVL 45

Application:

 

Characteristics:

General characteristics

          NVL45 was designed for conversion of  analog signals to digital codes of IBM PC type. The analog part of this device is based on ADC сhips of  AD9226 type, produced by the company " ANALOG DEVICES". Maximum sampling rate of this ADC is 60 MHz. Total conversion is executed in 4 clocks. So the apparatus delay for 1 selection is 80 ns. However the results of conversion can be read every 20 ns as capturing every new analog signal takes place every clock and conversion is executed continuously.

         The results of conversion are stored in NVL45 buffer memory. Selected data that will be stored is chosen by the program. Storage is executed from the maximum address till 0 address. Storage to the buffer memory begins with the 1st positive front of clock frequency after the "Start" signal. This signal is formed by the program when the captured selection is recorded or by external TTL signal.

        To reduce the speed of signal capture and consequently to increase the time of this capture you should use the provided opportunity to decrease the ADC clock frequency and execute measurement selection during data storage in the buffer memory. ADC bar frequency ranges: 60, 30, 15 or 7,5 MHz, coefficients ranges: 1/4, 1/8, 1/16... To increase the time of data capture you should use the whole memory for ADC signals capture of one channel.

The buffer memory of  NVL45 is almost of the same structure as 1M * 32. ADC codes of the 1st channel are stored in 11-0 bits , codes of the 2nd channel are stored in 27-16 bits.

            There are digital input ports: 8 bit and digital output port: 8 bit used to control NVL45 digital processes.

            The digital part of the device is based on PCI interface integrated controller.

            The controller realizes the further mentionned characteristics:

How to install NVL 45 (in PC)

       NVL45 is installed in a free PC slot. After the first start (when you have already installed NVL45) the installation of the device is reflected. The BIOS device identifies it as coprocessor. Vendor ID = 0x1999 и Device ID = 0x680C should be noted in the list.

       To make NVL45 function with Windows in the right way you should install “xdsps.sys” driver. This driver should be installed as common extra equipment. A disc with this driver is included in a set. After successful installation of this driver you will have the note "NVL45" in the list of Windows equipment.

            If there are no notes after trying to install the device it means: either the device is broken or it has already been inserted before. If the device has already been inserted there should be a note about this in the device manager. So you should look through "Other Devices" list in the manager of devices and find a note " Coprocessor". Then chose "Driver" and click "Update Driver". Then follow the operations described in the previous passages.

Programming NVL45

From the point of view of programming NVL45 is 2 addresses of I/O ports with 32 bit resolution each and 1M of 32 bit memory cells. The structure of the device NVL45 is formed through the I/O ports. Data of  the digital  ports is read and written through the I/O ports. The results of analog/digital conversion are stored in the memory cells of the device.

            The structure of the ports: 

Port address 5H

Resolution:

				W	W	W	W
31	30	29	28	27	26	25	24		Decimation while recording in memory
x	x	x	x	D3	D2	D1	D0

 x – are not used

D2  D1  D0 – coefficient of decimation

Code recorded in resolution D2..D0          coefficient of decimation   

1	1
2	2
3	4
4	8
5	16
6	32
7	64
8	128

D3 – Chosing the clock signal source

0 - internal clock generator
1 - external clock generator; its frequency is twice as high as the ADC frequency ( pin 28 of external input of the device)

				W	W	W	W
23	22	21	20	19	18	17	16		chosing the number of the commutator channel
x	C5	C4	C3	x	C2	C1	C0

x – not used

C5 C4 C3  - number of the 1st ADC commutator channel

C2 C1 C0  - number of the 2nd ADC commutator channel

				W	W	W	W
15	14	13	12	11	10	9	8		controlling the frequency devisor
x	S	I	ME	IN	UI	F1	F0

x – not used

S – controlling external start.
0 external start is banned
1 external start is executed by the front of EST signal on the pin 29 of external input

I – interruption control
0 interruption banned
1 interruption allowed

ME – 0 storage of the conversion results of both channels. odd selections of  the 1 channel conversion results are stored in the 1st channel memory; even selections are stored in the 2nd channel memory.

IN – 0 phase of the clok frequency of the 1st ADC coincides with the core frequency phase of the 2nd ADC., 1 phase of the 2nd ADC core frequency 180 degree differs from the core frequency phase of the 1st ADC.

UI – 0 input voltage +/- 1V., 1 input voltage +/- 2V.

F1,F0 – ADC sampling rate devisor 0 – 60 МHz, 1 – 30 МHz, 2 – 15 МHz, 3 –7,5 МHz

R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
7	6	5	4	3	2	1	0		digital I/O
IO7	IO6	IO5	IO4	IO3	IO2	IO1	IO0		resolution of  NVL45 digital I/O

Port adress 6H

Resolution:

| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | - are not used

| 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 |  9 |  8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | - buffer memory volume – maximum address of the RAM cell of NVL45. The ADC codes are captured from it and till 0.

This number is an order to start the catching (registration).

To synchronise NVL45 work with other devices there are 2 waveforms: STRT- output impulse, EST- external start signal.

Internally this signal is approached to log.1 level. Storage in the buffer memory will be moved to the growing front of  external start impulse. It is necessary to record the shape of the buffer memory before every external start. After external starting and before filling up the required buffer memory volume the signals of external starting are ignored.

The buffer memory of NVL45 is designed as 1М * 32. ADC codes of the 1st channel are preserved in resolution 11-0, ADC сodes of the 2nd channel in resolution 27-16 .Recording starts from the maximum address and continues till 0. Each cell is available for reading. You can read the results as many times as you want till the next order for catching (registration).

When the required volume of memory is filled up NVL45 makes interruption of the INTA# line and a bit of readiness which is on the 0 resolution of the word which is read on 6H port address. Log.0 in this resolution means that the buffer is filled up. Order for interruption is deleted when you execute the 1st reading from the memory of the device.