Device for registration, digital processing and synthesis of analog signals the sampling rate of which is up to 100 MHz.
                                                                 ADC100AS1
                             ADC 2õ12 bit, 80 MHz, DAC 9 bit, 80 MHz,
                                                                      MASTER PCI 32/33
3
Purposes of the inputs



Co-axis inputs
Input Purpose
J9 Output DAC
J14 External start input
J5 ADC input ,channel 2
J7 ADC input, channel 1
J2 input
Contact Purpose
1,3,5,7,9,11,13,15GND
14,16+ 3.3 V
2No connected
4,6 Extra output(not used)
8 Readiness
10 Temporary window
12 Temporary window inversion

J13 Input
Contact Purpose
1,3,5,7,9,11,13,15GND
2,4+ 3.3 V
6,8,10,12,16 Extra inputs(not used)
14 External start input
  • The signal Readiness ( J2 input, contact 8)- logic 1 on this input means the device is ready to begin the sampling process by  the + front  on the input of external starting ( J13 input contact 14, J14 input );
  • The signal Temporary Window ( J2 input, contact 10) - logic 1 level is maintained on this output during the sampling process, in any other time logic 0 level is maintained.  
  • The signal Temporary Window Inversion (J2 input , contact 12) - is an inverted signal Temporary Window.
  • The signal External Starting Input (J13 input, contact 14, J14 input) - + front of this signal starts the sampling process if there is logic 1 on the input Readiness after the first clock impulse from internal clock generator has reached the system (80 MHz).
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